晶合集成申请半导体西格玛沟槽专利，助力芯片制程优化，应对PMOS ...

合肥晶合集成电路股份有限公司（简称晶合集成）近日申请了一项名为“一种半导体器件中西格玛沟槽的制作方法”的专利，引发了行业关注。这项专利技术聚焦于半导体器件制造中的关键环节，旨在优化PMOS和NMOS的制程，解决两者高度差带来的潜在问题。这项技术革新，预示着国产芯片制造工艺的又一次进步。 解决PMOS/NMOS高度差的意义 PMOS和NMOS的高度差是影响芯片性能的重要因素之一。由于制造工艺的复杂性 ...
Nature

Overcoming the Leakage and Contact Resistance Challenges in Highly Scaled PMOS and NMOS ...

The Nature Index 2025 Research Leaders — previously known as Annual Tables — reveal the leading institutions and countries/territories in the natural and health sciences, according to their output in ...
sciencex

Towards a process flow for monolithic CFET transistor architectures

—The development of a process flow capable of demonstrating functionality of a monolithic complementary FET (CFET) transistor architecture is complex due to the need to vertically separate nMOS and ...
Nature

P-type NiOX dielectric-based CMOS inverter logic gate using enhancement-mode GaN nMOS and ...

The Nature Index 2025 Research Leaders — previously known as Annual Tables — reveal the leading institutions and countries/territories in the natural and health sciences, according to their output in ...
Semiconductor Engineering

Will CFETs Help The Industry Go Vertical?

Device scaling is getting much harder at each new process node. Even defining what it means is becoming a challenge. In the past, gate length and metal pitch went down and device density went up.