EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. – Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. — Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
Design-Reuse

Concept Engineering Introduces RTLvision PRO to Help Designers of IP-based System-on-Chip ...

FREIBURG, Germany - July 6, 2006 - Concept Engineering today announced the release of RTLvision¢â PRO, a customizable tool to help designers of intellectual property (IP)-based system-on-chip reduce ...
Design-Reuse

Bluespec Updates ESL Synthesis Toolset; Offers Improved Verilog RTL Output for Practical IP ...

WALTHAM, Mass.--May 11, 2006--Bluespec Inc. today released the latest version of its electronic system level (ESL) Synthesis software, offering a practical delivery vehicle for intellectual property ...