Designed a 16-bit array multiplier using carry save adders and drawing layout in Cadence. Improved performance of multiplier by pipelining multiplier using flip flops and latches.

MS in Electrical & Computer Engg. Seeking entry level positions in the digital hardware sector, i.e. FPGA emulation, VLSI/ASIC Design, Logic Design, Digital Systems & Embedded Systems.

The Department of Electronics and Communication Engineering, Shri Madhwa Vadiraja Institute of Technology and Management ...